This blog will go over some background about the power states which NVME defines under the power management capabilities that allows the host to control the power of the NVM subsytem.
The number of power states implemented by a controller is returned in the Number of Power States Supported (NPSS) Field in the Identify controller data structure. There may be up to 32 power states which might be supported
Below lets understand with some of the important terms associated with the power states . Let us consider different power states as different homes for an analogy for easy understanding
Power State 0 is associated with the maximum power, for eg, below is a snapshot from NVME spec depicting the power state descriptor
Autonomous power state transition
The host may be be able to configure the controller to directly transition between the power states
The Trade off – Latency and Performance
Different power-states helps in achieving efficiency and conserve power but that there is a slight interesting parameters to considers into “latency” and “performance”, the time it takes to move into a particular power stater and come out of it may impact the performance and the response time. Hence the vendors/manufacturers need to consider all these parameter.
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